Introduction and Vision
Modern detectors rapidly grow towards higher and higher granularity, channel density and signal rate capability. Until the 1980es the low granularity of detectors permitted readout electronics to be composed from discrete components, like individual transistors, while the use of integrated circuits was limited to commercially available parts (COTS = components of the shelf) like operational amplifiers.
With the advent of structured semiconductor detectors, like silicon micro strip detectors and silicon pixel detectors as well as of lithographically produced gaseous detectors like MSGCs (micro strip gaseous chamber) invented by A. Oed in 1988, a much higher density of readout channels was required.
Up to the present day, ASICs (application specific integrated circuits) are the only technology offering a sufficiently high level of integration to match the density and number of channels of these types of detectors.
Originally, integration started on a pure analogue level by combining several pre-amplifier and shaper circuits onto a silicon chip. These days, with detector systems becoming more and more complex, the drive for further integration added the need for a purely digital interface as well as signal processing (e.g. for data reduction, sparsification, pattern recognition or triggering) on the same chip, leading to analogue and digital circuitry on the same ASIC, thus termed Mixed Signal ASIC technology.
Likewise, today, even the signal generating detector is often integrated into the readout chip in pixel detectors, or, if the detector material is incompatible with the silicon process, directly bonded onto the chip in a post processing step.
With such pixel detector technology feasible and yet CMOS-Technology limited to comparatively small areas, there is a drive to allow for seamless tiling of pixel detectors, which immediately necessitates that signals need to be routed beyond the two-dimensional chip area through the silicon substrate into the third dimension. The enabling technology, called through silicon via (TSV) technology, is the essential basis for 3D integration. The technology evolving around 3D-integration is a hot issue in industry, where further integration in the third dimension will yet allow even higher densities e.g. in DRAM or flash memory devices or even higher bandwidth interconnect in complex digital systems by stacking and interconnecting various 2D chips. This technology may be exploited for highly integrated pixel detectors too. Towards this end designers need to get acquainted with the cutting edge 3D-integration software tools which are currently evolving and the corresponding few CMOS processes that already allow these integration steps.
In such 3D-architectures, designs grow ever more complex, and in turn also the tools needed for simulation and verification of a design, demand to be adapted to these new challenges. With individual chip realization costs exploding with the technological challenge, verification by simulation prior to chip submission is an essential part in chip design.
Motivation
The very high costs and uncertainty in tooling on one side, and the need of various Helmholtz-Centers, Universities and associated institutions to continue detector developments on the forefront of technology in various fields of physics provide the basis to start the introduction of these technologies as a common effort among the participating entities.
Goals and Activities
The primary goal of this work package is to contribute a 3D-integrated mixed-signal readout ASIC, manufactured in a deep sub-micron CMOS technology, suitable for integration in the Helmholtz-Cube.
Helmholtz-Cube will be a pixel detector, since this type of detector is used in most fields of modern physics, ranging from heavy ions and high energy physics to photon science and medical imaging. While such a detector can not fulfill the needs of individual experiments, it can show the feasibility of the technologies employed in these fields as a demonstrator.
Helmholtz-Cube is intended to incorporate most results from the various pillars of the Helmholtz Detector Portfolio, e.g. novel construction materials, advanced sensors, high density interconnects and 3D-mixed-signal ASICS. The basic idea here is to start from an existing detector design (e.g. a medipix based detector like LAMBDA) and to replace individual parts, like sensor, readout ASIC or the chip carrier individually with new components, before combining these to the final Helmholtz-Cube detector.
